25 µs
50 µs
ePWM
counter
PWM A/B
output
“a” “b” “c” “d”
Sampling
request
SEQ
interrupt
Case 1
I
1
,I
2
,I
3
“b”
I
1
,I
2
,I
3
V
1
,V
2
,V
3
“d”
V
1
,V
2
,V
3
Case 2
“b” “d”
Case 3
I
1
,I
2
I
1
,I
2
V
1
,V
2
,V
3
V
1
,V
2
,V
3
I
1
,I
2
,xI
1
,I
2
,x V
1
,V
2
,V
3
V
1
,V
2
,V
3
Sampling
request
SEQ
interrupt
Sampling
request
SEQ
interrupt
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ADC Interface
475
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
Case 3: Number of samples in the first and second sequences are equal (with dummy read)
• Mode 2 Interrupt operation (that is, Interrupt request occurs at every other EOS)
1. Sequencer is initialized with MAX_CONVn = 2 for I
1
, I
2
, and x(dummy sample).
2. At ISR "b" and "d", the following events take place :
a. Values I
1
, I
2
, x,V
1
, V
2
, and V
3
are read from ADC result registers.
b. The sequencer is reset.
3. Step 2 is repeated. Note that the third I-sample (x) is a dummy sample, and is not really required.
However, to minimize ISR overhead and CPU intervention, advantage is taken of the "every other"
Interrupt request feature of Mode 2.
Figure 7-14. Interrupt Operation During Sequenced Conversions
7.3.5 ADC to DMA Interface
The ADC result registers located in peripheral frame 0 (0x0B00 – 0x0B0F) are accessible by the DMA unit
on the F2833x. These registers can also be accessed by the CPU at the same time as the DMA without
bus contention. The result registers in peripheral frame 2 (0x7108 – 0x710F) are not accessible by the
DMA.
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