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ADC Circuit
449
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
(1)
Simultaneous mode generates 2 results for every ADC start of conversion.
Table 7-1. Clock Chain to the ADC
SYSCLK
OUT
HISPCLK ADCTRL3
[4-1]
ADCTRL1[7] ADCCLK ADCTRL1
[11-8]
Maximum Sustained Conversion Rate
150 MHz
HSPCP
= 3
ADCLKPS
= 0
CPS = 0
25 MHz
ACQ_PS = 0 SMODE_SEL = 0 SMODE_SEL = 1
(1)
150 MHz/
2 × 3 =
25 MHz
25 MHz 25 MHz
(1 / 25 MHz) ×
(ACQ_PS + 1)
Acquisition time = 40 ns
1 / (Acq time + 1 /
ADCCLK)
1 / (40ns + 40ns) =
12.5 MSPS
1 / (Acq time + 2 × (1 /
ADCCLK))
1/(40ns + 2(40ns)) =
8.33 MSPS
100 MHz
HSPCP = 2 ADCLKPS
= 2
CPS = 1
3.125
MHz
ACQ_PS = 15
1 / (Acq time + 1 /
ADCCLK)
1 / (5.12µs + 320ns) =
184 kSPS
1 / (Acq time + 2 × (1 /
ADCCLK))
1/(5.12µs + 2(320ns)) =
174 kSPS
100 MHz/
2 × 2 =
25 MHz
25/2 × 2 =
6.25 MHz
6.25 MHz/
2 × 1 =
3.125 MHz
(1 / 3.125 MHz) ×
(ACQ_PS + 1)
Acquisition time = 5.12
µs
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