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ADC Interface
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.3 ADC Interface
The following sub-sections describe the physical implementation of the ADC circuit. Topics that are
covered include:
• Trigger Sources
• ADC Sequencer State Machine
• ADC Interrupts
• ADC to DMA Interface
7.3.1 Input Trigger Description
Each sequencer has a set of trigger inputs that can be enabled/disabled. See Table 7-4 for the valid input
triggers for SEQ1, SEQ2, and cascaded SEQ.
Table 7-4. Input Triggers
SEQ1 (sequencer 1) SEQ2 (sequencer 2) Cascaded SEQ
Software trigger (software SOC) Software trigger (software SOC) Software trigger (software SOC)
ePWMx SOCA ePWMx SOCB ePWMx SOCA
XINT2_ADCSOC ePWMx SOCB
XINT2_ADCSOC
NOTE:
• An SOC trigger can initiate an autoconversion sequence whenever a sequencer is in an
idle state. An idle state is either CONV00 prior to receiving a trigger, or any state which
the sequencer lands on at the completion of a conversion sequence, i.e., when
SEQ_CNTR has reached a count of zero.
• If an SOC trigger occurs while a current conversion sequence is underway, it sets the
SOC_SEQn bit (which would have been cleared on the commencement of a previous
conversion sequence) in the ADCTRL2 register. If yet another SOC trigger occurs, it is
lost (i.e., when the SOC_SEQn bit is already set (SOC pending), subsequent triggers
will be ignored).
• Once triggered, the sequencer cannot be stopped/halted in mid sequence. The program
must either wait until an end-of-sequence (EOS) or initiate a sequencer reset, which
brings the sequencer immediately back to the idle start state (CONV00 for SEQ1 and
cascaded cases; CONV08 for SEQ2).
• When SEQ1/2 are used in cascaded mode, triggers going to SEQ2 are ignored, while
SEQ1 triggers are active. Cascaded mode can be viewed as SEQ1 with 16 states
instead of eight.
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