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eCAN Registers
803
SPRUI07–March 2020
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Controller Area Network (CAN)
13.8.3 Transmission-Request Set Register (CANTRS)
When mailbox n is ready to be transmitted, the CPU should set the TRS[n] bit to 1 to start the
transmission.
These bits are normally set by the CPU and cleared by the CAN module logic. The CAN module can set
these bits for a remote frame request. These bits are reset when a transmission is successful or aborted.
If a mailbox is configured as a receive mailbox, the corresponding bit in CANTRS is ignored unless the
receive mailbox is configured to handle remote frames. The TRS[n] bit of a receive mailbox is not ignored
if the RTR bit is set. Therefore, a receive mailbox (whose RTR is set) can send a remote frame if its TRS
bit is set. Once the remote frame is sent, the TRS[n] bit is cleared by the CAN module. Therefore, the
same mailbox can be used to request a data frame from another mode. If the CPU tries to set a bit while
the eCAN module tries to clear it, the bit is set.
Setting CANTRS[n] causes the particular message n to be transmitted. Several bits can be set
simultaneously. Therefore, all messages with the TRS bit set are transmitted in turn, starting with the
mailbox having the highest mailbox number (= highest priority), unless TPL bits dictate otherwise.
The bits in CANTRS are set by writing a 1 from the CPU. Writing a 0 has no effect. After power up, all bits
are cleared.
Figure 13-12. Transmission-Request Set Register (CANTRS)
31 0
TRS[31:0]
RS-0
LEGEND: RS = Read/Set; -n = value after reset
Table 13-11. Transmission-Request Set Register (CANTRS) Field Descriptions
Bit Field Value Description
31:0 TRS[31:0] Transmit-request-set bits
1 Setting TRSn commences the transmission of the message in that mailbox. Several bits can be set
simultaneously with all messages transmitted in turn.
0 No operation
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