Receiver Configuration
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-36. Register Bits Used to Set the Receive Frame Synchronization Mode (continued)
Register Bit Name Function Type
Reset
Value
SRGR2 15 GSYNC Sample rate generator clock synchronization mode R/W 0
If the sample rate generator creates a frame-synchronization signal
(FSG) that is derived from an external input clock, the GSYNC bit
determines whether FSG is kept synchronized with pulses on the FSR
pin.
GSYNC = 0 No clock synchronization is used: CLKG
oscillates without adjustment, and FSG pulses
every (FPER + 1) CLKG cycles.
GSYNC = 1 Clock synchronization is used. When a pulse is
detected on the FSR pin:
• CLKG is adjusted as necessary so that it is
synchronized with the input clock on the
MCLKR pin.
• FSG pulses FSG only pulses in response
to a pulse on the FSR pin. The frame-
synchronization period defined in FPER is
ignored.
For more details, see Section 12.4.3.
SPCR1 15 DLB Digital loopback mode R/W 0
DLB = 0 Digital loopback mode is disabled.
DLB = 1 Digital loopback mode is enabled. The receive
signals, including the receive frame-
synchronization signal, are connected internally
through multiplexers to the corresponding
transmit signals.
SPCR1 12-11 CLKSTP Clock stop mode R/W 00
CLKSTP = 0Xb Clock stop mode disabled; normal clocking for
non-SPI mode.
CLKSTP = 10b Clock stop mode enabled without clock delay.
The internal receive clock signal (MCLKR) and
the internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
CLKSTP = 11b Clock stop mode enabled with clock delay. The
internal receive clock signal (MCLKR) and the
internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
Table 12-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect
on the FSR Pin
DLB FSRM GSYNC
Source of Receive Frame
Synchronization FSR Pin Status
0 0 0 or 1 An external frame-synchronization signal
enters the McBSP through the FSR pin.
The signal is then inverted as determined
by FSRP before being used as internal
FSR.
Input
0 1 0 Internal FSR is driven by the sample rate
generator frame-synchronization signal
(FSG).
Output. FSG is inverted as determined by
FSRP before being driven out on the
FSR pin.
0 1 1 Internal FSR is driven by the sample rate
generator frame-synchronization signal
(FSG).
Input. The external frame-synchronization
input on the FSR pin is used to
synchronize CLKG and generate FSG
pulses.
1 0 0 Internal FSX drives internal FSR. High impedance
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