Transmitter Configuration
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
transmit register. The DMA PERINTFLG is edge-sensitive and will fail to recognize the XRDY, which is
continuously high.
For more details about McBSP reset conditions and effects, see Section 12.10.2.
12.9.3 Set the Transmitter Pins to Operate as McBSP Pins
To configure a pin for its McBSP function , you should configure the bits of the GPxMUXn register
appropriately. In addition to this, bits 12 and 13 of the PCR register must be set to 0. These bits are
defined as reserved.
12.9.4 Digital Loopback Mode
The DLB bit determines whether the digital loopback mode is on. DLB is described in Table 12-48.
Table 12-48. Register Bit Used to Enable/Disable the Digital Loopback Mode
Register Bit Name Function Type
Reset
Value
SPCR1 15 DLB Digital loopback mode R/W 0
DLB = 0 Digital loopback mode is disabled.
DLB = 1 Digital loopback mode is enabled.
12.9.4.1 Digital Loopback Mode
In the digital loopback mode, the receive signals are connected internally through multiplexers to the
corresponding transmit signals, as shown in Table 12-49. This mode allows testing of serial port code with
a single DSP device; the McBSP receives the data it transmits.
Table 12-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode
This Receive Signal
Is Fed Internally by
This Transmit Signal
DR (receive data) DX (transmit data)
FSR (receive frame synchronization) FSX (transmit frame synchronization)
MCLKR (receive clock) CLKX (transmit clock)
12.9.5 Clock Stop Mode
The CLKSTP bits determine whether the clock stop mode is on. CLKSTP is described in Table 12-50.
Table 12-50. Register Bits Used to Enable/Disable the Clock Stop Mode
Register Bit Name Function Type
Reset
Value
SPCR1 12-11 CLKSTP Clock stop mode R/W 00
CLKSTP = 0Xb Clock stop mode disabled; normal clocking for
non-SPI mode.
CLKSTP = 10b Clock stop mode enabled without clock delay
CLKSTP = 11b Clock stop mode enabled with clock delay
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