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XINTF Registers
851
SPRUI07–March 2020
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External Interface (XINTF)
14.6 XINTF Registers
Table 14-7 lists the memory-mapped registers for the
XINTF_CONFIGURATION_AND_CONTROL_REGISTER_MAPPING. All register offset addresses not
listed in Table 14-7 should be considered as reserved locations and the register contents should not be
modified.
(1)
XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
Table 14-7. XINTF Configuration and Control Register Mapping
Offset Acronym Register Name Size (x16) Section
83Dh XRESET XINTF Reset Register 2 Section 14.6.1
B20h XTIMING0 XINTF Timing Register, Zone 0 2 Section 14.6.2
B2Ch XTIMING6
(1)
XINTF Timing Register, Zone 6 2 Section 14.6.3
B2Eh XTIMING7 XINTF Timing Register, Zone 7 2 Section 14.6.4
B38h XBANK XINTF Bank Control Register 1 Section 14.6.5
B3Ah XREVISION XINTF Revision Register 1 Section 14.6.6
The individual timing parameters can be programmed into the XTIMING registers described in
Section 14.2.
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