Texas Instruments TMS320 2833 Series User Manual

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SPRUI07–March 2020
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Enhanced Capture (eCAP)
5.8.2.9 ECEINT Register (Offset = 16h) [reset = 0h]
ECEINT is shown in Figure 5-26 and described in Table 5-12.
Return to the Summary Table.
The interrupt enable bits (CEVT1, ...) block any of the selected events from generating an interrupt.
Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the
ECFRC/ECCLR registers.
The proper procedure for configuring peripheral modes and interrupts is as follows:
- Disable global interrupts
- Stop eCAP counter
- Disable eCAP interrupts
- Configure peripheral registers
- Clear spurious eCAP interrupt flags
- Enable eCAP interrupts
- Start eCAP counter
- Enable global interrupts
Figure 5-26. ECEINT Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CTR_EQ_CMP CTR_EQ_PRD CTROVF CEVT4 CEVT3 CEVT2 CEVT1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
Table 5-12. ECEINT Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h
Reserved
7 CTR_EQ_CMP R/W 0h
Counter Equal Compare Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Compare Equal as an Interrupt source
1h (R/W) = Enable Compare Equal as an Interrupt source
6 CTR_EQ_PRD R/W 0h
Counter Equal Period Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Period Equal as an Interrupt source
1h (R/W) = Enable Period Equal as an Interrupt source
5 CTROVF R/W 0h
Counter Overflow Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disabled counter Overflow as an Interrupt source
1h (R/W) = Enable counter Overflow as an Interrupt source
4 CEVT4 R/W 0h
Capture Event 4 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 4 as an Interrupt source
1h (R/W) = Capture Event 4 Interrupt Enable
3 CEVT3 R/W 0h
Capture Event 3 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 3 as an Interrupt source
1h (R/W) = Enable Capture Event 3 as an Interrupt source
2 CEVT2 R/W 0h
Capture Event 2 Interrupt Enable
Reset type: SYSRSn
0h (R/W) = Disable Capture Event 2 as an Interrupt source
1h (R/W) = Enable Capture Event 2 as an Interrupt source

Texas Instruments TMS320 2833 Series Specifications

General

Brand	Texas Instruments
Model	TMS320 2833 Series
Category	Controller
Language	English