www.ti.com
Transmitter Configuration
735
SPRUI07–March 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1
and FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted
down on every CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame
period value (FPER + 1) is also counting down. When this value reaches 0, FSG goes high, indicating a
new frame.
12.9.19 Transmit Clock Mode
Table 12-67 shows which register bits can set the Transmit Clock Mode.
Table 12-67. Register Bit Used to Set the Transmit Clock Mode
Register Bit Name Function Type
Reset
Value
PCR 9 CLKXM Transmit clock mode R/W 0
CLKXM = 0 The transmitter gets its clock signal from an
external source via the MCLKX pin.
CLKXM = 1 The MCLKX pin is an output pin driven by the
sample rate generator of the McBSP.
12.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
Table 12-68 shows how the CLKXM bit selects the transmit clock and the corresponding status of the
MCLKX pin. The polarity of the signal on the MCLKX pin is determined by the CLKXP bit.
Table 12-68. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the
MCLKX pin
CLKXM in
PCR Source of Transmit Clock MCLKX pin Status
0 Internal CLKX is driven by an external clock on the MCLKX pin.
CLKX is inverted as determined by CLKXP before being used.
Input
1 Internal CLKX is driven by the sample rate generator clock,
CLKG.
Output. CLKG, inverted as determined by CLKXP,
is driven out on CLKX.
12.9.19.2 Other Considerations
If the sample rate generator creates a clock signal (CLKG) that is derived from an external input clock, the
GSYNC bit determines whether CLKG is kept synchronized with pulses on the FSR pin. For more details,
see Section 12.4.3.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI
protocol. If the McBSP is a master, make sure that CLKXM = 1 so that CLKX is an output to supply the
master clock to any slave devices. If the McBSP is a slave, make sure that CLKXM = 0 so that CLKX is an
input to accept the master clock signal.
12.9.20 Transmit Clock Polarity
Table 12-69 shows which register bits set the Transmit Clock Polarity.
Table 12-69. Register Bit Used to Set Transmit Clock Polarity
Register Bit Name Function Type
Reset
Value
PCR 1 CLKXP Transmit clock polarity R/W 0
CLKXP = 0 Transmit data sampled on rising edge of CLKX.
CLKXP = 1 Transmit data sampled on falling edge of CLKX.
To Next Page
Loading...
Need help?
General
