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Register Descriptions
541
SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.9.23 SRC_ADDR_SHADOW Register (Offset = 1032h + [i * E3h]) [reset = 0h]
SRC_ADDR_SHADOW is shown in Figure 8-30 and described in Table 8-26.
Figure 8-30. SRC_ADDR_SHADOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0h R/W-0h
Table 8-26. SRC_ADDR_SHADOW Register Field Descriptions
Bit Field Type Reset Description
31-22 RESERVED R 0h
Reserved
21-0 ADDR R/W 0h 22-bit address value
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