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Emulation and Reset Considerations
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
• How to program McBSP response to a breakpoint in the high-level language debugger (see
Section 12.10.1)
• How to reset and initialize the various parts of the McBSP (see Section 12.10.2)
12.10.1 McBSP Emulation Mode
FREE and SOFT are special emulation bits in SPCR2 that determine the state of the McBSP when a
breakpoint is encountered in the high-level language debugger. If FREE = 1, the clock continues to run
upon a software breakpoint and data is still shifted out. When FREE = 1, the SOFT bit is a don't care.
If FREE = 0, the SOFT bit takes effect. If SOFT = 0 when breakpoint occurs, the clock stops immediately,
aborting a transmission. If SOFT = 1 and a breakpoint occurs while transmission is in progress, the
transmission continues until completion of the transfer and then the clock halts. These options are listed in
Table 12-70.
The McBSP receiver functions in a similar fashion. If a mode other than the immediate stop mode (SOFT
= FREE = 0) is chosen, the receiver continues running and an overrun error is possible.
Table 12-70. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2
FREE SOFT McBSP Emulation Mode
0 0 Immediate stop mode (reset condition)
The transmitter or receiver stops immediately in response to a breakpoint.
0 1 Soft stop mode
When a breakpoint occurs, the transmitter stops after completion of the current word. The receiver is
not affected.
1 0 or 1 Free run mode
The transmitter and receiver continue to run when a breakpoint occurs.
12.10.2 Resetting and Initializing McBSPs
This section discusses in greater depth the MCBSP Reset and Initialization configurations.
12.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
Table 12-71 shows the state of McBSP pins when the serial port is reset due to direct receiver or
transmitter reset on the 2833x device.
(1)
In Possible State(s) column, I = Input, O = Output, Z = High impedance. In the 28x family, at device reset, all I/Os default to
GPIO function and generally as inputs.
Table 12-71. Reset State of Each McBSP Pin
Pin Possible State(s)
(1)
State Forced by Device
Reset
State Forced by
Receiver/Transmitter Reset
Receiver reset (RRST = 0 and GRST = 1)
MDRx I GPIO-input Input
MCLKRx I/O/Z GPIO-input Known state if input; MCLKR running if output
MFSRx I/O/Z GPIO-input Known state if input; FSRP inactive state if output
Transmitter reset (XRST = 0 and GRST = 1)
MDXx O/Z GPIO Input High impedance
MCLKXx I/O/Z GPIO-input Known state if input; CLKX running if output
MFSXx I/O/Z GPIO-input Known state if input; FSXP inactive state if output
12.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
When the McBSP is reset in either of the above two ways, the machine is reset to its initial state, including
reset of all counters and status bits. The receive status bits include RFULL, RRDY, and RSYNCERR. The
transmit status bits include XEMPTY, XRDY, and XSYNCERR.
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