Peripheral Interrupt Expansion (PIE)
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SPRUI07–March 2020
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System Control and Interrupts
(1)
Not all register values are valid. The PROTSTART address value must be a multiple of the range value. For example: if the
block size is set to 4K, then the start address can only be at any 4K boundary.
Table 1-107. PROTRANGE Valid Values
Register Bits
(1)
Block Size Register Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
128 0x0001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
256 0x0003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
512 0x0007 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
1K 0x000F 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
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256K 0x0FFF 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
512K 0x1FFF 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1M 0x3FFF 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2M 0x7FFF 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4M 0xFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1.6 Peripheral Interrupt Expansion (PIE)
The peripheral interrupt expansion (PIE) block multiplexes numerous interrupt sources into a smaller set of
interrupt inputs. The PIE block can support 96 individual interrupts that are grouped into blocks of eight.
Each group is fed into one of 12 core interrupt lines (INT1 to INT12). Each of the 96 interrupts is
supported by its own vector stored in a dedicated RAM block that you can modify. The CPU, upon
servicing the interrupt, automatically fetches the appropriate interrupt vector. It takes nine CPU clock
cycles to fetch the vector and save critical CPU registers. Therefore, the CPU can respond quickly to
interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt
can be enabled/disabled within the PIE block.
1.6.1 Overview of the PIE Controller
The 28x CPU supports one nonmaskable interrupt (NMI) and 16 maskable prioritized interrupt requests
(INT1-INT14, RTOSINT, and DLOGINT) at the CPU level. The 28x devices have many peripherals and
each peripheral is capable of generating one or more interrupts in response to many events at the
peripheral level. Because the CPU does not have sufficient capacity to handle all peripheral interrupt
requests at the CPU level, a centralized peripheral interrupt expansion (PIE) controller is required to
arbitrate the interrupt requests from various sources such as peripherals and other external pins.
The PIE vector table is used to store the address (vector) of each interrupt service routine (ISR) within the
system. There is one vector per interrupt source including all MUXed and nonMUXed interrupts. You
populate the vector table during device initialization and you can update it during operation.
1.6.1.1 Interrupt Operation Sequence
Figure 1-78 shows an overview of the interrupt operation sequence for all multiplexed PIE interrupts.
Interrupt sources that are not multiplexed are fed directly to the CPU.
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