Register Descriptions
www.ti.com
546
SPRUI07–March 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Direct Memory Access (DMA) Module
8.9.28 DST_BEG_ADDR Register (Offset = 103Ch + [i * E3h]) [reset = 0h]
DST_BEG_ADDR is shown in Figure 8-35 and described in Table 8-31.
Figure 8-35. DST_BEG_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BEGADDR
R-0h R-0h
Table 8-31. DST_BEG_ADDR Register Field Descriptions
Bit Field Type Reset Description
31-22 RESERVED R 0h
Reserved
21-0 BEGADDR R 0h 22-bit address value
To Next Page
Loading...
Need help?
General
