Texas Instruments TMS320 2833 Series User Manual

Mathtables
andfunctions
Bootloader
functions
Resetvector
CPUvectortable
64x16
0x3FE000
0x3FFFFF
0x3FFFC0
Resetfetchedfromherewhen
VMAP=1
Othervectorsfetchedfromherewhen
VMAP=1,ENPIE=0
Boot ROM Memory Map www.ti.com
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Boot ROM
• Exp Min/Max Table, IQMath Table
– Table size: 120 words
– Q format: Q1 - Q30
– Contents: 32-bit Min and Max values for each Q value
• Exp Coefficient Table, IQMath Table
– Table size: 20 words
– Q format: Q31
– Contents: 32-bit coefficients for calculating exp (X) using a Taylor series
2.1.2 CPU Vector Table
A CPU vector table, Figure 2-2, resides in boot ROM memory from address 0x3F E000 - 0x3F FFFF. This
vector table is active after reset when VMAP = 1, ENPIE = 0 (PIE vector table disabled).
Figure 2-2. Vector Table Map
(1) The VMAP bit is located in Status Register 1 (ST1). VMAP is always 1 on reset. It can be changed after reset
by software, however the normal operating mode will be to leave VMAP = 1.
(2) The ENPIE bit is located in the PIECTRL register. The default state of this bit at reset is 0, which disables the
Peripheral Interrupt Expansion block (PIE).
The only vector that will normally be handled from the internal boot ROM memory is the reset vector
located at 0x3F FFC0. The reset vector is factory programmed to point to the InitBoot function stored in
the boot ROM. This function starts the bootload process. A series of checking operations is performed on
select General-Purpose I/O (GPIO) pins to determine which boot mode to use. This boot mode selection is
described in Section 2.2.9 of this document.
The remaining vectors in the boot ROM are not used during normal operation. After the boot process is
complete, you should initialize the Peripheral Interrupt Expansion (PIE) vector table and enable the PIE
block. From that point on, all vectors, except reset, will be fetched from the PIE module and not the CPU
vector table shown in Table 2-1.
For TI silicon debug and test purposes the vectors located in the boot ROM memory point to locations in
the M0 SARAM block as described in Table 2-1. During silicon debug, you can program the specified
locations in M0 with branch instructions to catch any vectors fetched from boot ROM. This is not required
for normal device operation.

Texas Instruments TMS320 2833 Series Specifications

General

Brand	Texas Instruments
Model	TMS320 2833 Series
Category	Controller
Language	English