McBSP Registers
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-85. Transmit Control 2 Register (XCR2) Field Descriptions (continued)
Bit Field Value Description
2 XFIG Transmit frame-synchronization ignore bit. If a frame-synchronization pulse starts the transfer of a new
frame before the current frame is fully transmitted, this pulse is treated as an unexpected frame-
synchronization pulse.
Setting XFIG causes the serial port to ignore unexpected frame-synchronization pulses during
transmission.
0 Frame-synchronization detect. An unexpected FSX pulse causes the transmitter to discard the content
of XSR[1,2]. The transmitter:
1. Aborts the present transmission
2. Sets XSYNCERR in SPCR2
3. Begins a new transmission from DXR[1,2]. If new data was written to DXR[1,2] since the last
DXR[1,2]-to-XSR[1,2] copy, the current value in XSR[1,2] is lost. Otherwise, the same data is
transmitted.
1 Frame-synchronization ignore. An unexpected FSX pulse is ignored. Transmission continues
uninterrupted.
1-0 XDATDLY 0-3h Transmit data delay bits. XDATDLY specifies a data delay of 0, 1, or 2 transmit clock cycles after frame
synchronization and before the transmission of the first bit of the frame. For more details, see
Section 12.9.13.
0 0-bit data delay
1h 1-bit data delay
2h 2-bit data delay
3h Reserved (do not use)
Table 12-86. Frame Length Formula for Transmit Control 2 Register (XCR2)
XPHASE XFRLEN1 XFRLEN2 Frame Length
0 0 ≤ XFRLEN1 ≤ 127 Not used (XFRLEN1 + 1) words
1 0 ≤ XFRLEN1 ≤ 127 0 ≤ XFRLEN2 ≤ 127 (XFRLEN1 + 1) + (XFRLEN2 + 1) words
12.15.7 Sample Rate Generator Registers (SRGR1 and SRGR2)
Each McBSP has two sample rate generator registers, SRGR1 (Table 12-87) and SRGR2 (Table 12-88).
The sample rate generator can generate a clock signal (CLKG) and a frame-synchronization signal (FSG).
The registers SRGR1 and SRGR2 enable you to:
• Select the input clock source for the sample rate generator (CLKSM, in conjunction with the SCLKME
bit of PCR)
• Divide down the frequency of CLKG (CLKGDV)
• Select whether internally-generated transmit frame-synchronization pulses are driven by FSG or by
activity in the transmitter (FSGM).
• Specify the width of frame-synchronization pulses on FSG (FWID) and specify the period between
those pulses (FPER)
When an external source (via the MCLKR or MCLKX pin) provides the input clock source for the sample
rate generator:
• If the CLKX/MCLKR pin is used, the polarity of the input clock is selected with CLKXP/CLKRP of PCR.
• The GSYNC bit of SRGR2 allows you to make CLKG synchronized to an external frame-
synchronization signal on the FSR pin, so that CLKG is kept in phase with the input clock.
12.15.7.1 Sample Rate Generator 1 Register (SRGR1)
The sample rate generator 1 register is shown in Figure 12-75 and described in Table 12-87.
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