McBSP Sample Rate Generator
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
12.4.1.1 Clock Generation in the Sample Rate Generator
The sample rate generator can produce a clock signal (CLKG) for use by the receiver, the transmitter, or
both. Use of the sample rate generator to drive clocking is controlled by the clock mode bits (CLKRM and
CLKXM) in the pin control register (PCR). When a clock mode bit is set to 1 (CLKRM = 1 for reception,
CLKXM = 1 for transmission), the corresponding data clock (CLKR for reception, CLKX for transmission)
is driven by the internal sample rate generator output clock (CLKG).
The effects of CLKRM = 1 and CLKXM = 1 on the McBSP are partially affected by the use of the digital
loopback mode and the clock stop (SPI) mode, respectively, as described in Table 12-4. The digital
loopback mode (described in Section 12.8.4) is selected with the DLB bit of SPCR1. The clock stop mode
(described in Section 12.7.2) is selected with the CLKSTP bits of SPCR1.
When using the sample rate generator as a clock source, make sure the sample rate generator is enabled
(GRST = 1).
Table 12-4. Effects of DLB and CLKSTP on Clock Modes
Mode Bit Settings Effect
CLKRM = 1 DLB = 0
(Digital loopback mode disabled)
CLKR is an output pin driven by the sample rate generator output clock
(CLKG).
DLB = 1
(Digital loopback mode enabled)
CLKR is an output pin driven by internal CLKX. The source for CLKX
depends on the CLKXM bit.
CLKXM = 1 CLKSTP = 00b or 01b
(Clock stop (SPI) mode disabled)
CLKX is an output pin driven by the sample rate generator output clock
(CLKG).
CLKSTP = 10b or 11b
(Clock stop (SPI) mode enabled)
The McBSP is a master in an SPI system. Internal CLKX drives internal
CLKR and the shift clocks of any SPI-compliant slave devices in the
system. CLKX is driven by the internal sample rate generator.
12.4.1.2 Choosing an Input Clock
The sample rate generator must be driven by an input clock signal from one of the three sources
selectable with the SCLKME bit of PCR and the CLKSM bit of SRGR2 (see Table 12-5). When CLKSM =
1, the minimum divide down value in CLKGDV bits is 1. CLKGDV is described in Section 12.4.1.4.
Table 12-5. Choosing an Input Clock for the Sample Rate Generator with the
SCLKME and CLKSM Bits
SCLKME CLKSM Input Clock for Sample Rate Generator
0 0 Reserved
0 1 LSPCLK
1 0 Signal on MCLKR pin
1 1 Signal on MCLKX pin
12.4.1.3 Choosing a Polarity for the Input Clock
As shown in Figure 12-18, when the input clock is received from a pin, you can choose the polarity of the
input clock. The rising edge of CLKSRG generates CLKG and FSG, but you can determine which edge of
the input clock causes a rising edge on CLKSRG. The polarity options and their effects are described in
Table 12-6.
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