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Texas Instruments TMS320 2833 Series User Manual

Texas Instruments TMS320 2833 Series
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Registers
297
SPRUI07March 2020
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Copyright © 2020, Texas Instruments Incorporated
Enhanced Pulse Width Modulator (ePWM) Module
Table 3-23. Time-Base Counter Register (TBCTR) Field Descriptions
Bits Name Value Description
15-0 TBCTR 0000-
FFFF
Reading these bits gives the current time-base counter value.
Writing to these bits sets the current time-base counter value. The update happens as soon as the write
occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed.
Figure 3-64. Time-Base Control Register (TBCTL)
15 14 13 12 10 9 8
FREE, SOFT PHSDIR CLKDIV HSPCLKDIV
R/W-0 R/W-0 R/W-0 R/W-0,0,1
7 6 5 4 3 2 1 0
HSPCLKDIV SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE
R/W-0,0,1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-11
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-24. Time-Base Control Register (TBCTL) Field Descriptions
Bit Field Value Description
15:14 FREE, SOFT Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
00 Stop after the next time-base counter increment or decrement
01 Stop when counter completes a whole cycle:
Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
1X Free run
13 PHSDIR Phase Direction Bit.
This bit is only used when the time-base counter is configured in the up-down-count mode. The
PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization
event occurs and a new phase value is loaded from the phase (TBPHS) register. This is
irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
0 Count down after the synchronization event.
1 Count up after the synchronization event.
12:10 CLKDIV Time-base Clock Prescale Bits
These bits determine part of the time-base clock prescale value.
TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
000 /1 (default on reset)
001 /2
010 /4
011 /8
100 /16
101 /32
110 /64
111 /128

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Texas Instruments TMS320 2833 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320 2833 Series
CategoryController
LanguageEnglish

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