Unexpected frame synchronization
RBR1 to DRR1(B)
C0C1C2C3C4C5C6C7B4B5B6B7A0A1
RSYNCERR
RRDY
DR
FSR
CLKR
Read from DRR1(C)RBR1 to DRR1 copy(C)Read from DRR1(A)RBR1 to DRR1 copy(A)
McBSP Exception/Error Conditions
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
progress when the pulse occurs:
– The FSR pulse is the first after the receiver is enabled (RRST = 1 in SPCR1).
– The FSR pulse is the first after DRR[1,2] is read, clearing a receiver full (RFULL = 1 in SPCR1)
condition.
– The serial port is in the interpacket intervals. The programmed data delay for reception
(programmed with the RDATDLY bits in RCR2) may start during these interpacket intervals for the
first bit of the next word to be received. Thus, at maximum frame frequency, frame synchronization
can still be received 0 to 2 clock cycles before the first bit of the synchronized frame.
• Case 3: Unexpected receive frame synchronization with RFIG = 0 (frame-synchronization pulses not
ignored). Unexpected frame-synchronization pulses can originate from an external source or from the
internal sample rate generator.
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
received, this pulse is treated as an unexpected frame-synchronization pulse, and the receiver sets the
receive frame-synchronization error bit (RSYNCERR) in SPCR1. RSYNCERR can be cleared only by a
receiver reset or by a write of 0 to this bit.
If you want the McBSP to notify the CPU of receive frame-synchronization errors, you can set a special
receive interrupt mode with the RINTM bits of SPCR1. When RINTM = 11b, the McBSP sends a
receive interrupt (RINT) request to the CPU each time that RSYNCERR is set.
12.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
Figure 12-30 shows an unexpected receive frame-synchronization pulse during normal operation of the
serial port, with time intervals between data packets. When the unexpected frame-synchronization pulse
occurs, the RSYNCERR bit is set, the reception of data B is aborted, and the reception of data C begins.
In addition, if RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU.
Figure 12-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception
12.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
Each frame transfer can be delayed by 0, 1, or 2 MCLKR cycles, depending on the value in the RDATDLY
bits of RCR2. For each possible data delay, Figure 12-25 shows when a new frame-synchronization pulse
on FSR can safely occur relative to the last bit of the current frame.
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