Texas Instruments TMS320 2833 Series

Configuring Lead, Active, and Trail Wait States www.ti.com
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SPRUI07–March 2020
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External Interface (XINTF)
14.4.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then the following requirement must be met:
Lead: LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 0 ≥ 0 ≥ 1 ≥ 0 ≥0 0, 1
Examples of valid and invalid timings when not sampling XREADY:
(1)
No hardware to detect illegal XTIMING configurations
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid
(1)
0 0 0 0 0 0 0, 1
Valid 1 0 0 1 0 0 0, 1
14.4.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then the
following requirements must be met:
1 Lead: LR ≥ × t
c(XTIM)
LW ≥ t
c(XTIM)
2 Active: AR ≥ 2 × t
c(XTIM)
AW ≥ 2 × t
c(XTIM)
NOTE: Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
(1)
No hardware to detect illegal XTIMING configurations
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 1 ≥ 0 ≥ 1 ≥ 1 ≥ 0 0, 1
(1)
Examples of valid and invalid timings when using synchronous XREADY:
(1)
No hardware to detect illegal XTIMING configurations
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid
(1)
0 0 0 0 0 0 0, 1
Invalid
(1)
1 0 0 1 0 0 0, 1
Valid 1 1 0 1 1 0 0, 1