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Registers
325
SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
Figure 3-88. Event-Trigger Force Register (ETFRC)
15 8
Reserved
R-0
7 4 3 2 1 0
Reserved SOCB SOCA Reserved INT
R-0 R/W-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-48. Event-Trigger Force Register (ETFRC) Field Descriptions
Bits Name Value Description
15-4 Reserved Reserved
3 SOCB SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL
register. The ETFLG[SOCB] flag bit will be set regardless.
0 Has no effect. Always reads back a 0.
1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test
purposes.
2 SOCA SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL
register. The ETFLG[SOCA] flag bit will be set regardless.
0 Writing 0 to this bit will be ignored. Always reads back a 0.
1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test
purposes.
1 Reserved 0 Reserved
0 INT INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register.
The INT flag bit will be set regardless.
0 Writing 0 to this bit will be ignored. Always reads back a 0.
1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.
3.4.8 Proper Interrupt Initialization Procedure
When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to
spurious events due to the ePWM registers not being properly initialized. The proper procedure for
initializing the ePWM peripheral is as follows:
1. Disable global interrupts (CPU INTM flag)
2. Disable ePWM interrupts
3. Set TBCLKSYNC=0
4. Initialize peripheral registers
5. Set TBCLKSYNC=1
6. Clear any spurious ePWM flags (including PIEIFR)
7. Enable ePWM interrupts
8. Enable global interrupts
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