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SPRUI07–March 2020
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Serial Communications Interface (SCI)
10.2 Architecture
The major elements used in full-duplex operation are shown in Figure 10-2 and include:
• A transmitter (TX) and its major registers (upper half of Figure 10-2)
– SCITXBUF — transmitter data buffer register. Contains data (loaded by the CPU) to be transmitted
– TXSHF register — transmitter shift register. Accepts data from register SCITXBUF and shifts data
onto the SCITXD pin, one bit at a time
• A receiver (RX) and its major registers (lower half of Figure 10-2)
– RXSHF register — receiver shift register. Shifts data in from SCIRXD pin, one bit at a time
– SCIRXBUF — receiver data buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into register RXSHF and then into registers SCIRXBUF and
SCIRXEMU
• A programmable baud generator
• Control and status registers
The SCI receiver and transmitter can operate either independently or simultaneously.
10.3 SCI Module Signal Summary
A summarized description of each SCI signal name is shown in Table 10-1.
Table 10-1. SCI Module Signal Summary
Signal Name Description
External signals
SCIRXD SCI Asynchronous Serial Port receive data
SCITXD SCI Asynchronous Serial Port transmit data
Control
Baud clock LSPCLK Prescaled clock
Interrupt signals
TXINT Transmit interrupt
RXINT Receive Interrupt
10.4 Configuring Device Pins
The GPIO mux registers must be configured to connect this peripheral to the device pins. To avoid
glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding
GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.
Some IO functionality is defined by GPIO register settings independent of this peripheral. For input
signals, the GPIO input qualification should be set to asynchronous mode by setting the appropriate
GPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.
See the GPIO chapter for more details on GPIO mux and settings.
10.5 Multiprocessor and Asynchronous Communication Modes
The SCI has two multiprocessor protocols, the idle-line multiprocessor mode (see Section 10.8) and the
address-bit multiprocessor mode (see Section 10.9). These protocols allow efficient data transfer between
multiple processors.
The SCI offers the universal asynchronous receiver/transmitter (UART) communications mode for
interfacing with many popular peripherals. The asynchronous mode (see Section 10.10) requires two lines
to interface with many standard devices such as terminals and printers that use RS-232-C formats. Data
transmission characteristics include:
• One start bit
• One to eight data bits
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