SCI Multiprocessor Communication
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SPRUI07–March 2020
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Serial Communications Interface (SCI)
Sleep Bit
All processors on the serial link set the SCI SLEEP bit (bit 2 of SCICTL1) to 1 so that they are interrupted
only when the address byte is detected. When a processor reads a block address that corresponds to the
CPU device address as set by your application software, your program must clear the SLEEP bit to enable
the SCI to generate an interrupt on receipt of each data byte.
Although the receiver still operates when the SLEEP bit is 1, it does not set RXRDY, RXINT, or any of the
receiver error status bits to 1 unless the address byte is detected and the address bit in the received
frame is a 1 (applicable to address-bit mode). The SCI does not alter the SLEEP bit; your software must
alter the SLEEP bit.
10.7.1 Recognizing the Address Byte
A processor recognizes an address byte differently, depending on the multiprocessor mode used. For
example:
• The idle-line mode (Section 10.8) leaves a quiet space before the address byte. This mode does not
have an extra address/data bit and is more efficient than the address-bit mode for handling blocks that
contain more than ten bytes of data. The idle-line mode should be used for typical non-multiprocessor
SCI communication.
• The address-bit mode (Section 10.9) adds an extra bit (that is, an address bit) into every byte to
distinguish addresses from data. This mode is more efficient in handling many small blocks of data
because, unlike the idle mode, it does not have to wait between blocks of data. However, at a high
transmit speed, the program is not fast enough to avoid a 10-bit idle in the transmission stream.
10.7.2 Controlling the SCI TX and RX Features
The multiprocessor mode is software selectable via the ADDR/IDLE MODE bit (SCICCR, bit 3). Both
modes use the TXWAKE flag bit (SCICTL1, bit 3), RXWAKE flag bit (SCIRXST, bit1), and the SLEEP flag
bit (SCICTL1, bit 2) to control the SCI transmitter and receiver features of these modes.
10.7.3 Receipt Sequence
In both multiprocessor modes, the receive sequence is as follows:
1. At the receipt of an address block, the SCI port wakes up and requests an interrupt (bit number 1
RX/BK INT ENA-of SCICTL2 must be enabled to request an interrupt). It reads the first frame of the
block, which contains the destination address.
2. A software routine is entered through the interrupt and checks the incoming address. This address
byte is checked against its device address byte stored in memory.
3. If the check shows that the block is addressed to the device CPU, the CPU clears the SLEEP bit and
reads the rest of the block. If not, the software routine exits with the SLEEP bit still set, and does not
receive interrupts until the next block start.
10.8 Idle-Line Multiprocessor Mode
In the idle-line multiprocessor protocol (ADDR/IDLE MODE bit=0), blocks are separated by having a
longer idle time between the blocks than between frames in the blocks. An idle time of ten or more high-
level bits after a frame indicates the start of a new block. The time of a single bit is calculated directly from
the baud value (bits per second). The idle-line multiprocessor communication format is shown in
Figure 10-4 (ADDR/IDLE MODE bit is bit 3 of SCICCR).
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