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ADC Registers
485
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.4.4 ADCCHSELSEQ1 Register (Offset = 3h) [reset = 0h]
ADCCHSELSEQ1 is shown in Figure 7-18 and described in Table 7-14.
Figure 7-18. ADCCHSELSEQ1 Register
15 14 13 12 11 10 9 8
CONV03 CONV02
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CONV01 CONV00
R/W-0h R/W-0h
Table 7-14. ADCCHSELSEQ1 Register Field Descriptions
Bit Field Type Reset Description
15-12 CONV03 R/W 0h
11-8 CONV02 R/W 0h
7-4 CONV01 R/W 0h
3-0 CONV00 R/W 0h
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