eCAP Registers
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SPRUI07–March 2020
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Enhanced Capture (eCAP)
5.8.2.12 ECFRC Register (Offset = 19h) [reset = 0h]
ECFRC is shown in Figure 5-29 and described in Table 5-15.
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Capture Interrupt Force Register
Figure 5-29. ECFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CTR_CMP CTR_PRD CTROVF CEVT4 CEVT3 CEVT2 CEVT1 RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h
Table 5-15. ECFRC Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h
Reserved
7 CTR_CMP R-0/W1S 0h
Force Counter Equal Compare Interrupt. This event is only active in
APWM mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR=CMP flag.
6 CTR_PRD R-0/W1S 0h
Force Counter Equal Period Interrupt. This event is only active in
APWM mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CTR=PRD flag.
5 CTROVF R-0/W1S 0h
Force Counter Overflow.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 to this bit sets the CTROVF flag.
4 CEVT4 R-0/W1S 0h
Force Capture Event 4. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT4 flag.
3 CEVT3 R-0/W1S 0h
Force Capture Event 3. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT3 flag.
2 CEVT2 R-0/W1S 0h
Force Capture Event 2. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Writing a 1 sets the CEVT2 flag.
1 CEVT1 R-0/W1S 0h
Force Capture Event 1. This event is only active in CAP mode.
Reset type: SYSRSn
0h (R/W) = No effect. Always reads back a 0.
1h (R/W) = Sets the CEVT1 flag.
0 RESERVED R 0h
Reserved
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