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ADC Registers
487
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.4.6 ADCCHSELSEQ3 Register (Offset = 5h) [reset = 0h]
ADCCHSELSEQ3 is shown in Figure 7-20 and described in Table 7-16.
Figure 7-20. ADCCHSELSEQ3 Register
15 14 13 12 11 10 9 8
CONV11 CONV10
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CONV09 CONV08
R/W-0h R/W-0h
Table 7-16. ADCCHSELSEQ3 Register Field Descriptions
Bit Field Type Reset Description
15-12 CONV11 R/W 0h
11-8 CONV10 R/W 0h
7-4 CONV09 R/W 0h
3-0 CONV08 R/W 0h
Each of the 4-bit fields, CONVxx, selects one of the 16 MUXed analog input ADC channels for an
autosequenced conversion.
Table 7-17. CONVnn Bit Values and the ADC Input
Channels Selected
CONVnn Value ADC Input Channel Selected
0000 ADCINA0
0001 ADCINA1
0010 ADCINA2
0011 ADCINA3
0100 ADCINA4
0101 ADCINA5
0110 ADCINA6
0111 ADCINA7
1000 ADCINB0
1001 ADCINB1
1010 ADCINB2
1011 ADCINB3
1100 ADCINB4
1101 ADCINB5
1110 ADCINB6
1111 ADCINB7
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