Texas Instruments TMS320 2833 Series User Manual

RX FIFO_15
…
RX FIFO_1
RX FIFO_0
TX FIFO_0
TX FIFO_1
...
TX FIFO_15
SPIRXBUF
SPIDAT
SPITXBUF
SPISOMI
SPISIMO
RXFFST
TXFFST
=?
RXFFIL
TXFFIL
<?
>?
16
RXFFOVF
OVERRUN_FLAG
INT_FLAG
OVRNINTENA
SPIINTENA
TXFFIENA
SPIFFENA
RXFFIENA
SPIRXINT
SPITXINT
1
0
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Serial Peripheral Interface (SPI)
SPITXINT
The SPITXINT interrupt is not available when the SPI is operating in non-FIFO mode.
In FIFO mode, the SPITXINT behavior is similar to the SPIRXINT. SPITXINT is generated upon a match
condition between the current transmit FIFO status (TXFFST) and the transmit FIFO interrupt level
(TXFFIL). If TXFFST is less than or equal to TXFFIL, the transmit FIFO interrupt flag (TXFFINT) will be
set. SPITXINT will be triggered in the PIE block if TXFFINT is set and the transmit FIFO interrupt is
enabled in the SPI module (TXFFIENA = 1).
Figure 9-2 and Table 9-2 show how these control bits influence the SPI interrupt generation.
Figure 9-2. SPI Interrupt Flags and Enable Logic Generation
(1)
In non-FIFO mode, SPIRXINT is the same name as the SPIINT interrupt in 28x devices.
Table 9-2. SPI Interrupt Flag Modes
FIFO Options
SPI Interrupt
Source
Interrupt Flags Interrupt Enables
FIFO Enable
(SPIFFENA)
Interrupt Line
(1)
SPI without FIFO
Receive overrun RXOVRN OVRNINTENA 0 SPIRXINT
Data receive SPIINT SPIINTENA 0 SPIRXINT
Transmit empty SPIINT SPIINTENA 0 SPIRXINT
SPI FIFO mode
FIFO receive RXFFIL RXFFIENA 1 SPIRXINT
Transmit empty TXFFIL TXFFIENA 1 SPITXINT

Texas Instruments TMS320 2833 Series Specifications

General

Brand	Texas Instruments
Model	TMS320 2833 Series
Category	Controller
Language	English