ePWM Submodules
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SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
The key signals associated with the counter-compare submodule are described in Table 3-6.
Table 3-6. Counter-Compare Submodule Key Signals
Signal Description of Event Registers Compared
CTR = CMPA Time-base counter equal to the active counter-compare A value TBCTR = CMPA
CTR = CMPB Time-base counter equal to the active counter-compare B value TBCTR = CMPB
CTR = PRD Time-base counter equal to the active period.
Used to load active counter-compare A and B registers from the
shadow register
TBCTR = TBPRD
CTR = ZERO Time-base counter equal to zero.
Used to load active counter-compare A and B registers from the
shadow register
TBCTR = 0x0000
3.2.3.3 Operational Highlights for the Counter-Compare Submodule
The counter-compare submodule is responsible for generating two independent compare events based on
two compare registers:
1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCTR = CMPA).
2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCTR = CMPB).
For up-count or down-count mode, each event occurs only once per cycle. For up-down-count mode each
event occurs twice per cycle if the compare value is between 0x0000-TBPRD and once per cycle if the
compare value is equal to 0x0000 or equal to TBPRD. These events are fed into the action-qualifier
submodule where they are qualified by the counter direction and converted into actions if enabled. Refer
to Section 3.2.4.1 for more details.
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing
provides a way to keep updates to the registers synchronized with the hardware. When shadowing is
used, updates to the active registers only occur at strategic points. This prevents corruption or spurious
operation due to the register being asynchronously modified by software. The memory address of the
active register and the shadow register is identical. Which register is written to or read from is determined
by the CMPCTL[SHDWAMODE] and CMPCTL[SHDWBMODE] bits. These bits enable and disable the
CMPA shadow register and CMPB shadow register respectively. The behavior of the two load modes is
described below:
Shadow Mode:
The shadow mode for the CMPA is enabled by clearing the CMPCTL[SHDWAMODE] bit and the shadow
register for CMPB is enabled by clearing the CMPCTL[SHDWBMODE] bit. Shadow mode is enabled by
default for both CMPA and CMPB.
If the shadow register is enabled then the content of the shadow register is transferred to the active
register on one of the following events as specified by the CMPCTL[LOADAMODE] and
CMPCTL[LOADBMODE] register bits:
• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).
• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
• Both CTR = PRD and CTR = Zero
Only the active register contents are used by the counter-compare submodule to generate events to be
sent to the action-qualifier.
Immediate Load Mode:
If immediate load mode is selected (i.e., TBCTL[SHADWAMODE] = 1 or TBCTL[SHADWBMODE] = 1),
then a read from or a write to the register will go directly to the active register.
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