Registers
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SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
3.4.2 Counter-Compare Submodule Registers
Figure 3-66 through Figure 3-69 and Table 3-26 through Table 3-28 illustrate the counter-compare
submodule control and status registers.
Figure 3-66. Counter-Compare A Register (CMPA)
15 0
CMPA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-26. Counter-Compare A Register (CMPA) Field Descriptions
Bits Name Description
15-0 CMPA The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the
values are equal, the counter-compare module generates a "time-base counter equal to counter compare A"
event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions.
These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of
the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers
include:
• Do nothing; the event is ignored.
• Clear: Pull the EPWMxA and/or EPWMxB signal low
• Set: Pull the EPWMxA and/or EPWMxB signal high
• Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this register is
shadowed.
• If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically go to the
shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event will load the active
register from the shadow register.
• Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is currently full.
• If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go directly to
the active register, that is the register actively controlling the hardware.
• In either mode, the active and shadow registers share the same memory map address.
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