Flash and OTP Memory Blocks
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SPRUI07–March 2020
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System Control and Interrupts
1.1.4 Flash and OTP Registers
The flash and OTP memory can be configured by the registers shown in Table 1-1. The configuration
registers are all EALLOW protected. The bit descriptions are in Figure 1-4 through Figure 1-10.
(1)
These registers are EALLOW protected. See Section 1.5.2 for information.
(2)
These registers are protected by the Code Security Module (CSM). See Section 1.2 for more information.
(3)
These registers should be left in their default state.
Table 1-1. Flash/OTP Configuration Registers
Name
(1) (2)
Address Size (x16) Description Bit Description
FOPT 0x0A80 1 Flash Option Register Figure 1-4
Reserved 0x0A81 1 Reserved
FPWR 0x0A82 1 Flash Power Modes Register Figure 1-5
FSTATUS 0x0A83 1 Status Register Figure 1-6
FSTDBYWAIT
(3)
0x0A84 1 Flash Sleep To Standby Wait Register Figure 1-7
FACTIVEWAIT
(3)
0x0A85 1 Flash Standby To Active Wait Register Figure 1-8
FBANKWAIT 0x0A86 1 Flash Read Access Wait State Register Figure 1-9
FOTPWAIT 0x0A87 1 OTP Read Access Wait State Register Figure 1-10
NOTE: The flash configuration registers should not be written to by code that is running from OTP or
flash memory or while an access to flash or OTP may be in progress. All register accesses
to the flash registers should be made from code executing outside of flash/OTP memory and
an access should not be attempted until all activity on the flash/OTP has completed. No
hardware is included to protect against this.
To summarize, you can read the flash registers from code executing in flash/OTP; however,
do not write to the registers.
CPU write access to the flash configuration registers can be enabled only by executing the EALLOW
instruction. Write access is disabled when the EDIS instruction is executed. This protects the registers
from spurious accesses. Read access is always available. The registers can be accessed through the
JTAG port without the need to execute EALLOW. See Section 1.5.2 for information on EALLOW
protection. These registers support both 16-bit and 32-bit accesses.
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