ADC Circuit
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.2.4 Power-up Sequence and Power Modes
7.2.4.1 Power-up Sequencing
The ADC resets to the ADC off state. When powering up the ADC, use the following sequence:
1. If external reference is desired, enable this mode using bits 15-14 in the ADCREFSEL Register. This
mode must be enabled before band gap is powered.
2. Power up the reference, bandgap, and analog circuits together by setting bits 7-5 (ADCBGRFDN[1:0],
ADCPWDN) in the ADCTRL3 register.
3. Before performing the first conversion, a delay of 5 ms is required.
When powering down the ADC, all three bits can be cleared simultaneously. The ADC power level must
be controlled via software and they are independent of the state of the device power modes.
Sometimes it is desirable to power down the ADC while leaving the band-gap and reference powered by
clearing the ADCPWDN bit only. When the ADC is re-powered, a delay of 1 ms is required after this bit is
set before performing any conversions.
NOTE: The 2833x ADC requires a 5-ms delay after all of the circuits are powered up. This differs
from the 281x ADC.
7.2.4.2 Power Modes
The ADC supports three separate power sources each controlled by independent bits in the ADCTRL3
register. These three bits combine to make up three power levels: ADC power up, ADC power down, and
ADC off.
Table 7-3. Power Options
Power Level ADCBGRFDN1 ADCBGRFDN0 ADCPWDN
ADC power-up 1 1 1
ADC power-down 1 1 0
ADC off 0 0 0
Reserved 1 0 X
Reserved 0 1 X
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