SCI Enhanced Features
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SPRUI07–March 2020
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Serial Communications Interface (SCI)
(1)
FIFO mode TXSHF is directly loaded after delay value, TXBUF is not used.
(2)
RXERR can be set by BRKDT, FE, OE, PE flags. In FIFO mode, BRKDT interrupt is only through RXERR flag
Table 10-4. SCI Interrupt Flags
FIFO Options
(1)
SCI Interrupt Source Interrupt Flags Interrupt Enables FIFO Enable
SCIFFENA
Interrupt Line
SCI without FIFO Receive error RXERR
(2)
RXERRINTENA 0 RXINT
Receive break BRKDT RX/BKINTENA 0 RXINT
Data receive RXRDY RX/BKINTENA 0 RXINT
Transmit empty TXRDY TXINTENA 0 TXINT
SCI with FIFO Receive error and receive
break
RXERR RXERRINTENA 1 RXINT
FIFO receive RXFFIL RXFFIENA 1 RXINT
Transmit empty TXFFIL TXFFIENA 1 TXINT
Auto-baud Auto-baud detected ABD Don’t care x TXINT
10.13.2 SCI Auto-Baud
Most SCI modules do not have an auto-baud detect logic built-in hardware. These SCI modules are
integrated with embedded controllers whose clock rates are dependent on PLL reset values. Often
embedded controller clocks change after final design. In the enhanced feature set this module supports an
autobaud-detect logic in hardware. The following section explains the enabling sequence for autobaud-
detect feature.
10.13.3 Autobaud-Detect Sequence
Bits ABD and CDC in SCIFFCT control the autobaud logic. The SCIRST bit should be enabled to make
autobaud logic work.
If ABD is set while CDC is 1, which indicates auto-baud alignment, SCI transmit FIFO interrupt will occur
(TXINT). After the interrupt service CDC bit has to be cleared by software. If CDC remains set even after
interrupt service, there should be no repeat interrupts.
1. Enable autobaud-detect mode for the SCI by setting the CDC bit (bit 13) in SCIFFCT and clearing the
ABD bit (Bit 15) by writing a 1 to ABDCLR bit (bit 14).
2. Initialize the baud register to be 1 or less than a baud rate limit of 500 Kbps.
3. Allow SCI to receive either character "A" or "a" from a host at the desired baud rate. If the first
character is either "A" or "a", the autobaud- detect hardware will detect the incoming baud rate and set
the ABD bit.
4. The auto-detect hardware will update the baud rate register with the equivalent baud value hex. The
logic will also generate an interrupt to the CPU.
5. Respond to the interrupt clear ADB bit by writing a 1 to ABD CLR (bit 14) of SCIFFCT register and
disable further autobaud locking by clearing CDC bit by writing a 0.
6. Read the receive buffer for character "A" or "a" to empty the buffer and buffer status.
7. If ABD is set while CDC is 1, which indicates autobaud alignment, the SCI transmit FIFO interrupt will
occur (TXINT). After the interrupt service CDC bit must be cleared by software.
NOTE: At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver
and connector performance. While normal serial communications may work well, this slew
rate may limit reliable autobaud detection at higher baud rates (typically beyond 100k baud)
and cause the auto-baudlock feature to fail.
To avoid this, the following is recommended:
• Achieve a baud-lock between the host and 28x SCI boot loader using a lower
baud rate.
• The host may then handshake with the loaded 28x application to set the SCI
baud rate register to the desired higher baud rate.
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