eCAN Registers
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SPRUI07–March 2020
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Controller Area Network (CAN)
13.8.15.4 Mailbox Interrupt Level Register (CANMIL)
Each of the 32 mailboxes may initiate an interrupt on one of the two interrupt lines. Depending on the
setting in the mailbox interrupt level register (CANMIL), the interrupt is generated on ECAN0INT (MILn =
0) or on line ECAN1INT (MIL[n] = 1).
Figure 13-29. Mailbox Interrupt Level Register (CANMIL)
31 0
MIL.31:0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-25. Mailbox Interrupt Level Register (CANMIL) Field Descriptions
Bit Field Value Description
31:0 MIL.31:0 Mailbox interrupt level. These bits allow any mailbox interrupt level to be selected individually.
1 The mailbox interrupt is generated on interrupt line 1.
0 The mailbox interrupt is generated on interrupt line 0.
13.8.16 Overwrite Protection Control Register (CANOPC)
If there is an overflow condition for mailbox n (RMP[n] is set to 1 and a new receive message would fit for
mailbox n), the new message is stored depending on the settings in the CANOPC register. If the
corresponding bit OPC[n] is set to 1, the old message is protected against being overwritten by the new
message; thus, the next mailboxes are checked for a matching ID. If no other mailbox is found, the
message is lost without further notification. If the bit OPC[n] is cleared to 0, the old message is overwritten
by the new one. This is notified by setting the receive message lost bit RML[n].
For read/write operations, only 32-bit access is supported.
Figure 13-30. Overwrite Protection Control Register (CANOPC)
31 0
OPC.31:0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-26. Overwrite Protection Control Register (CANOPC) Field Descriptions
Bit Field Value Description
31:0 OPC.31:0 Overwrite protection control bits
1 1 If the bit OPC[n] is set to 1, an old message stored in that mailbox is protected against being
overwritten by the new message.
0 0 If the bit OPC[n] is not set, the old message can be overwritten by a new one.
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