Register Descriptions
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.9.4 PRIORITYCTRL1 Register (Offset = 1004h) [reset = 0h]
PRIORITYCTRL1 is shown in Figure 8-11 and described in Table 8-6.
Figure 8-11. PRIORITYCTRL1 Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED CH1PRIORITY
R-0h R/W-0h
Table 8-6. PRIORITYCTRL1 Register Field Descriptions
Bit Field Type Reset Description
15-1 RESERVED R 0h
Reserved
0 CH1PRIORITY R/W 0h DMA Ch1 Priority: This bit selects whether channel 1 has higher
priority or not: Channel priority can only be changed when all
channels are disabled.
A priority reset should be performed before restarting channels after
changing priority.
0h = Same priority as all other channels
1h = Highest priority channel
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