ePWM Submodules
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SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is
delayed by. For example, the formula to calculate falling-edge-delay and rising-edge-delay are:
FED = DBFED × T
TBCLK
RED = DBRED × T
TBCLK
Where T
TBCLK
is the period of TBCLK, the prescaled version of SYSCLKOUT.
For convenience, delay values for various TBCLK options are shown in Table 3-15.
Table 3-15. Dead-Band Delay Values in μS as a Function of DBFED and DBRED
Dead-Band Value Dead-Band Delay in μS
DBFED, DBRED TBCLK = SYSCLKOUT/1 TBCLK = SYSCLKOUT /2 TBCLK = SYSCLKOUT/4
1 0.01 μS 0.02 μS 0.04 μS
5 0.05 μS 0.10 μS 0.20 μS
10 0.10 μS 0.20 μS 0.40 μS
100 1.00 μS 2.00 μS 4.00 μS
200 2.00 μS 4.00 μS 8.00 μS
300 3.00 μS 6.00 μS 12.00 μS
400 4.00 μS 8.00 μS 16.00 μS
500 5.00 μS 10.00 μS 20.00 μS
600 6.00 μS 12.00 μS 24.00 μS
700 7.00 μS 14.00 μS 28.00 μS
800 8.00 μS 16.00 μS 32.00 μS
900 9.00 μS 18.00 μS 36.00 μS
1000 10.00 μS 20.00 μS 40.00 μS
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