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ADC Interface
473
SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
Table 7-7. Values for ADCCHSELSEQn (MAX_CONV1 set to 2)
Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0
7103h V
1
I
3
I
2
I
1
ADCCHSELSEQ1
7104h x x V
3
V
2
ADCCHSELSEQ2
7105h x x x x ADCCHSELSEQ3
7106h x x x x ADCCHSELSEQ4
Table 7-8. Values After Second Autoconversion Session
Buffer Register ADC Conversion Result Buffer
ADCRESULT0 I
1
ADCRESULT1 I
2
ADCRESULT2 I
3
ADCRESULT3 V
1
ADCRESULT4 V
2
ADCRESULT5 V
3
ADCRESULT6 x
ADCRESULT7 x
ADCRESULT8 x
ADCRESULT9 x
ADCRESULT10 x
ADCRESULT11 x
ADCRESULT12 x
ADCRESULT13 x
ADCRESULT14 x
ADCRESULT15 x
7.3.3.2 Sequencer Override Feature
In normal operation, sequencers SEQ1, SEQ2 or cascaded SEQ1 help to convert selected ADC channels
and store them in the respective ADCRESULTn registers, sequentially. The sequence naturally wraps
around at the end of the MAX_CONVn setting. With the sequencer override feature, the natural
wraparound of the sequencers can be controlled in software. The sequencer override feature is controlled
by bit 5 of the ADC Control Register 1 (ADCCTRL1).
For example, assume the SEQ_OVRD bit is 0 and the ADC is in cascaded-sequencer, continuous-
conversion mode with MAX_CONV1 set to 7. Normally, the sequencer would increment sequentially and
update up to ADCRESULT7 register with ADC conversions and wraps around to 0. At the end of the
ADCRESULT7 register update, the relevant interrupt flag would be set.
With the SEQ_OVRD bit set to 1, the sequencer updates seven result registers and does not wrap around
to 0. Instead, the sequencer will increment sequentially and update the ADCRESULT8 register onwards
until the ADCRESULT15 register is reached. After updating ADCRESULT15 register, the natural wrap
around to 0 will occur. This feature treats the result registers (0-15) like a FIFO for sequential data capture
from the ADC. This feature is very helpful to capture ADC data when ADC conversions are done at the
maximum data rate.
Recommendations and caution on sequencer override feature:
• After reset, SEQ_OVRD bit will be 0; therefore the sequencer override feature remains disabled.
• When SEQ _OVRD bit is set for all nonzero values of MAX_CONVn, the related interrupt flag bit will
be set for every MAX_CONVn count of result register update.
• For example, if ADCMAXCONV is set to 3, then the interrupt flag for the selected sequencer will be set
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