ADC Interface
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
every four result register updates. The wraparound always occurs at the end of the sequencer (i.e.,
after ADCRESULT15 register update in cascaded sequencer mode).
• This will be functional in conversions using SEQ1, SEQ2, and cascaded sequencers using SEQ1.
• It is recommended that this feature not be enabled/controlled dynamically within the program. Always
enable this feature during the ADC module initialization.
• In continuous-conversion mode with sequencer changes, the ADC channel address uses the preset
values in CONVxx registers. If continuous conversions of the same channel are needed then all the
CONVxx registers should have the same channel address.
• In continuous-conversion mode, if a sequencer reset is needed: set CONT_RUN bit to 0, wait 2 cycles
in the ADC Clock domain, then reset the sequencer. CONT_RUN can then be set back to 1.
• For example, to get 16 contiguous samples for the ADCINA0 channel using the sequencer override
feature, all 16 CONVxx registers should be set to 0x0000.
7.3.4 Interrupt Operation During Sequenced Conversions
There are two ADC interrupt signals that correspond to each sequencer, SEQ1 INT and SEQ2 INT. Each
interrupt can be selectively enabled/disabled by its corresponding INT_ENA_SEQ# bit in the ADCTRL2
register. The status(active = 1) of each interrupt is presented in the ADCST register as INT_SEQ2 and
INT_SEQ1 bits respectively.
Once an interrupt is latched in either INT_SEQ1 or INT_SEQ2, it must be cleared in order for another
interrupt to be generated to the C28x CPU/PIE module. The interrupt clear bit is also located in ADCST as
INT_SEQ1_CLR and INT_SEQ2_CLR. Finally, cascaded sequencer mode only uses SEQ1 INT, as this
mode treats SEQ1 as the lone 16-state sequencer for the ADC.
The sequencer can generate interrupts under two operating modes. These modes are determined by the
Interrupt-Mode-Enable control bits in ADCTRL2.
A variation of Example 7-6 can be used to show how interrupt mode 1 and mode 2 are useful under
different operating conditions.
Case 1: Number of samples in the first and second sequences are not equal
• Mode 1 Interrupt operation (that is, Interrupt request occurs at every EOS)
1. Sequencer is initialized with MAX_CONVn = 1 for converting I
1
and I
2
2. At ISR "a", MAX_CONVn is changed to 2 (by software) for converting V
1
, V
2
, and V
3
3. At ISR "b", the following events take place :
a. MAX_CONVn is changed to 1 again for converting I
1
and I
2
.
b. Values I
1
, I
2
, V
1
, V
2
, and V
3
are read from ADC result registers.
c. The sequencer is reset.
4. Steps 2 and 3 are repeated. Note that the interrupt flag is set every time SEQ_CNTR reaches zero
and both interrupts are recognized.
Case 2: Number of samples in the first and second sequences are equal
• Mode 2 Interrupt operation (that is, Interrupt request occurs at every other EOS)
1. Sequencer is initialized with MAX_CONVn = 2 for converting I
1
, I
2
, and I
3
(or V
1
, V
2
, and V
3
).
2. At ISR "b" and "d", the following events take place :
a. Values I
1
, I
2
, I
3
,V
1
, V
2
, and V
3
are read from ADC result registers.
b. The sequencer is reset.
3. Step 2 is repeated.
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