Receiver Configuration
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-40. Register Bits Used to Set the Receive Clock Mode (continued)
Register Bit Name Function Type
Reset
Value
SPCR1 12-11 CLKSTP Clock stop mode R/W 00
CLKSTP = 0Xb Clock stop mode disabled; normal clocking for
non-SPI mode.
CLKSTP = 10b Clock stop mode enabled without clock delay.
The internal receive clock signal (MCLKR) and
the internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
CLKSTP = 11b Clock stop mode enabled with clock delay. The
internal receive clock signal (MCLKR) and the
internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
12.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
Table 12-41 shows how you can select various sources to provide the receive clock signal and affect the
MCLKR pin. The polarity of the signal on the MCLKR pin is determined by the CLKRP bit.
In the digital loopback mode (DLB = 1), the transmit clock signal is used as the receive clock signal.
Also, in the clock stop mode, the internal receive clock signal (MCLKR) and the internal receive frame-
synchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX.
Table 12-41. Receive Clock Signal Source Selection
DLB in
SPCR1
CLKRM in
PCR Source of Receive Clock MCLKR Pin Status
0 0 The MCLKR pin is an input driven by an
external clock. The external clock signal is
inverted as determined by CLKRP before
being used.
Input
0 1 The sample rate generator clock (CLKG)
drives internal MCLKR.
Output. CLKG, inverted as determined by CLKRP,
is driven out on the MCLKR pin.
1 0 Internal CLKX drives internal MCLKR. To
configure CLKX, see Section 12.9.19.
High impedance
1 1 Internal CLKX drives internal MCLKR. To
configure CLKX, see Section 12.9.19.
Output. Internal MCLKR (same as internal CLKX)
is inverted as determined by CLKRP before being
driven out on the MCLKR pin.
12.8.18 Receive Clock Polarity
Table 12-42. Register Bit Used to Set Receive Clock Polarity
Register Bit Name Function Type
Reset
Value
PCR 0 CLKRP Receive clock polarity R/W 0
CLKRP = 0 Receive data sampled on falling edge of MCLKR
CLKRP = 1 Receive data sampled on rising edge of MCLKR
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