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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.9.17 SRC_WRAP_COUNT Register (Offset = 102Bh + [i * E3h]) [reset = 0h]
SRC_WRAP_COUNT is shown in Figure 8-24 and described in Table 8-20.
Figure 8-24. SRC_WRAP_COUNT Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRAPCOUNT
R/W-0h
Table 8-20. SRC_WRAP_COUNT Register Field Descriptions
Bit Field Type Reset Description
15-0 WRAPCOUNT R/W 0h These bits indicate the current wrap counter value:
0000h = Wrap complete
0001h = 1 burst left
0002h = 2 burst left
....
FFFFh = 65535 burst left
The above values represent the state of the counter at the HALT
conditions.
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