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Register Descriptions
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SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.9.25 SRC_ADDR Register (Offset = 1036h + [i * E3h]) [reset = 0h]
SRC_ADDR is shown in Figure 8-32 and described in Table 8-28.
Figure 8-32. SRC_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0h R-0h
Table 8-28. SRC_ADDR Register Field Descriptions
Bit Field Type Reset Description
31-22 RESERVED R 0h
Reserved
21-0 ADDR R 0h 22-bit address value
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