For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.
CLKR/CLKX
FSR/FSX
DR/DX
Last bit of
current frame
Earliest possible
time to begin transfer
of next frame
www.ti.com
Multichannel Selection Modes
685
SPRUI07–March 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Figure 12-31. Proper Positioning of Frame-Synchronization Pulses
12.6 Multichannel Selection Modes
This section discusses the multichannel selection modes for the McBSP.
12.6.1 Channels, Blocks, and Partitions
A McBSP channel is a time slot for shifting in/out the bits of one serial word. Each McBSP supports up to
128 channels for reception and 128 channels for transmission.
In the receiver and in the transmitter, the 128 available channels are divided into eight blocks that each
contain 16 contiguous channels (see Table 12-8 through Table 12-10) :
• It is possible to have two receive partitions (A & B) and 8 transmit partitions (A – H).
• McBSP can transmit/receive on selected channels.
• Each channel partition has a dedicated channel-enable register. Each bit controls whether data flow is
allowed or prevented in one of the channels assigned to that partition.
• There are three transmit multichannel modes and one receive multichannel mode.
Table 12-8. Block - Channel Assignment
Block Channels
0 0 -15
1 16 - 31
2 32 - 47
3 48 - 63
4 64 - 79
5 80 - 95
6 96 - 111
7 112 - 127
To Next Page
Loading...
Need help?
General
