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I2C Registers
633
SPRUI07–March 2020
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Inter-Integrated Circuit Module (I2C)
11.6.2 I2C_REGS Registers
Table 11-8 lists the I2C_REGS registers. All register offset addresses not listed in Table 11-8 should be
considered as reserved locations and the register contents should not be modified.
Table 11-8. I2C_REGS Registers
Offset Acronym Register Name Write Protection Section
0h I2COAR I2C Own address Go
1h I2CIER I2C Interrupt Enable Go
2h I2CSTR I2C Status Go
3h I2CCLKL I2C Clock low-time divider Go
4h I2CCLKH I2C Clock high-time divider Go
5h I2CCNT I2C Data count Go
6h I2CDRR I2C Data receive Go
7h I2CSAR I2C Slave address Go
8h I2CDXR I2C Data Transmit Go
9h I2CMDR I2C Mode Go
Ah I2CISRC I2C Interrupt Source Go
Bh I2CEMDR I2C Extended Mode Go
Ch I2CPSC I2C Prescaler Go
20h I2CFFTX I2C FIFO Transmit Go
21h I2CFFRX I2C FIFO Receive Go
Complex bit access types are encoded to fit into small table cells. Table 11-9 shows the codes that are
used for access types in this section.
Table 11-9. I2C_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R
-0
Read
Returns 0s
Write Type
W W Write
W1C W
1C
Write
1 to clear
W1S W
1S
Write
1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
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