Registers
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SPRUI07–March 2020
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Enhanced Pulse Width Modulator (ePWM) Module
Figure 3-82. Trip-Zone Clear Register (TZCLR)
15 8
Reserved
R-0
7 3 2 1 0
Reserved OST CBC INT
R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-42. Trip-Zone Clear Register (TZCLR) Field Descriptions
Bits Name Value Description
15-3 Reserved Reserved
2 OST Clear Flag for One-Shot Trip (OST) Latch
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
1 CBC Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
0 INT Global Interrupt Clear Flag
0 Has no effect. Always reads back a 0.
1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the
TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.
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