Operational Description of HRPWM
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SPRUI07–March 2020
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High-Resolution Pulse Width Modulator (HRPWM)
4.2.2 Configuring the HRPWM
Once the ePWM has been configured to provide conventional PWM of a given frequency and polarity, the
HRPWM is configured by programming the HRCNFG register located at offset address 20h. This register
provides configuration options for the following key operating modes :
Edge Mode — The MEP can be programmed to provide precise position control on the rising edge (RE),
falling edge (FE) or both edges (BE) at the same time. FE and RE are used for power topologies
requiring duty cycle control, while BE is used for topologies requiring phase shifting, e.g., phase
shifted full bridge.
Control Mode — The MEP is programmed to be controlled either from the CMPAHR register (duty cycle
control) or the TBPHSHR register (phase control). RE or FE control mode should be used with
CMPAHR register. BE control mode should be used with TBPHSHR register.
Shadow Mode — This mode provides the same shadowing (double buffering) option as in regular PWM
mode. This option is valid only when operating from the CMPAHR register and should be chosen to
be the same as the regular load option for the CMPA register. If TBPHSHR is used, then this option
has no effect.
4.2.3 Principle of Operation
The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps (see device-specific
data sheet for typical MEP step size). The MEP works with the TBM and CCM registers to be certain that
time steps are optimally applied and that edge placement accuracy is maintained over a wide range of
PWM frequencies, system clock frequencies and other operating conditions. Table 4-3 Table 4-3shows
the typical range of operating frequencies supported by the HRPWM.
(1)
System frequency = SYSCLKOUT, that is, CPU clock. TBCLK =SYSCLKOUT.
(2)
Table data based on a MEP time resolution of 180 ps (this is an example value, see the device-specific data sheet for MEP
limits.
(3)
MEP steps applied = T
SYSCLKOUT
/180 ps in this example.
(4)
PWM minimum frequency is based on a maximum period value, that is, TBPRD = 65535. PWM mode is asymmetrical up-count.
(5)
Resolution in bits is given for the maximum PWM frequency stated.
Table 4-3. Relationship Between MEP Steps, PWM Frequency and Resolution
System
(MHz)
MEP Steps Per
SYSCLKOUT
(1) (2) (3)
PWM MIN
(Hz)
(4)
PWM MAX
(MHz)
Res. @ MAX
(Bits)
(5)
60.0 93 916 3.00 10.9
70.0 79 1068 3.50 10.6
80.0 69 1221 4.00 10.4
90.0 62 1373 4.50 10.3
100.0 56 1526 5.00 10.1
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