Texas Instruments TMS320 2833 Series User Manual

GPBDAT
(latch)
GPBCLEAR
GPBTOGGLE
GPBSEL1
Qual
GPBMUX1
SYSCLKOUT
High
Impedance
Output
Control
GPIO32,
GPIO33
Pins
PU
XRS
0
=
Input
,
1
=
Output
Sync
GPBDIR
(latch)
01
11
01
GPBCTRL
2
2
10
Perpheral1input
N/C
(defaultonreset)
GPIO32/33_OUT
(defaultonreset)
GPBPUD
0 = enablePU
1 = disablePU
(disabledafterreset)
async
(asyncdisable
whenlow)
0x
1x
11
10
Peripheral2input
Peripheral3input
GPBSET
(defaultonreset)
3samples
6samples
00
00
XRS
DefaultatReset
External
interrupt
MUX
GPIOXINT6SEL
GPIOXINT7SEL
GPIOXINT5SEL
GPIOXINT4SEL
GPIOXINT3SEL
PIE
GPBDAT (read)
01
Perpheral1output
11
10
Peripheral2output
Peripheral3output
00
01
11
10
Peripheral2outputenable
Peripheral3outputenable
00
SDAA/SCLA (I2Coutputenable)
SDAA/SCLA (I2Cdataout)
GPIO32/33-DIR
www.ti.com General-Purpose Input/Output (GPIO)
89
SPRUI07–March 2020
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System Control and Interrupts
Figure 1-42. GPIO32, GPIO33 Multiplexing Diagram
A The GPIOINENCLK bit in the PCLKCR3 register does not affect the above GPIOs (I2C pins) since the pins are bi-
directional.
B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode).
Any state will get flushed by the circuit eventually.

Texas Instruments TMS320 2833 Series Specifications

General

Brand	Texas Instruments
Model	TMS320 2833 Series
Category	Controller
Language	English