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Register Descriptions
531
SPRUI07–March 2020
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Direct Memory Access (DMA) Module
8.9.13 TRANSFER_COUNT Register (Offset = 1027h + [i * E3h]) [reset = 0h]
TRANSFER_COUNT is shown in Figure 8-20 and described in Table 8-16.
Figure 8-20. TRANSFER_COUNT Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANSFERCOUNT
R/W-0h
Table 8-16. TRANSFER_COUNT Register Field Descriptions
Bit Field Type Reset Description
15-0 TRANSFERCOUNT R/W 0h These bits specify the current transfer counter value:
0000h = 0 bursts left to transfer
0001h = 1 burst left to transfer
0002h = 2 bursts left to transfer
...
FFFFh = 65535 bursts left to transfer
The above values represent the state of the counter at the HALT
conditions.
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