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McBSP Registers
753
SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
Table 12-78. Serial Port Control 2 Register (SPCR2) Field Descriptions (continued)
Bit Field Value Description
0 XRST Transmitter reset bit. You can use XRST to take the McBSP transmitter into and out of its reset state.
This bit has a negative polarity; XRST = 0 indicates the reset state.
To read about the effects of a transmitter reset, see Section 12.10.2.
0 If you read a 0, the transmitter is in its reset state.
If you write a 0, you reset the transmitter.
1 If you read a 1, the transmitter is enabled.
If you write a 1, you enable the transmitter by taking it out of its reset state.
12.15.5 Receive Control Registers (RCR[1, 2])
Each McBSP has two receive control registers, RCR1 (Table 12-79) and RCR2 (Table 12-81). These
registers enable you to:
• Specify one or two phases for each frame of receive data (RPHASE)
• Define two parameters for phase 1 and (if necessary) phase 2: the serial word length (RWDLEN1,
RWDLEN2) and the number of words (RFRLEN1, RFRLEN2)
• Choose a receive companding mode, if any (RCOMPAND)
• Enable or disable the receive frame-synchronization ignore function (RFIG)
• Choose a receive data delay (RDATDLY)
12.15.5.1 Receive Control Register 1 (RCR1)
The receive control register 1 (RCR1) is shown in Figure 12-71 and described in Table 12-79.
Figure 12-71. Receive Control Register 1 (RCR1)
15 14 8
Reserved RFRLEN1
R-0 R/W-0
7 5 4 0
RWDLEN1 Reserved
R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12-79. Receive Control Register 1 (RCR1) Field Descriptions
Bit Field Value Description
15 Reserved 0 Reserved bits (not available for your use). They are read-only bits and return 0s when read.
14-8 RFRLEN1 0-7Fh Receive frame length 1 (1 to 128 words). Each frame of receive data can have one or two phases,
depending on value that you load into the RPHASE bit. If a single-phase frame is selected, RFRLEN1 in
RCR1 selects the number of serial words (8, 12, 16, 20, 24, or 32 bits per word) in the frame. If a dual-
phase frame is selected, RFRLEN1 determines the number of serial words in phase 1 of the frame, and
RFRLEN2 in RCR2 determines the number of words in phase 2 of the frame. The 7-bit RFRLEN fields
allow up to 128 words per phase. See Table 12-80 for a summary of how you determine the frame
length. This length corresponds to the number of words or logical time slots or channels per frame-
synchronization period.
Program the RFRLEN fields with [w minus 1], where w represents the number of words per phase. For
example, if you want a phase length of 128 words in phase 1, load 127 into RFRLEN1.
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