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Texas Instruments TMS320 2833 Series User Manual

Texas Instruments TMS320 2833 Series
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eCAN Registers
805
SPRUI07March 2020
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Copyright © 2020, Texas Instruments Incorporated
Controller Area Network (CAN)
13.8.6 Abort-Acknowledge Register (CANAA)
If the transmission of the message in mailbox n was aborted, the bit AA[n] is set and the AAIF
(CANGIF.14) bit is set, which may generate an interrupt if enabled.
The bits in CANAA are reset by writing a 1 from the CPU. Writing a 0 has no effect. If the CPU tries to
reset a bit and the CAN tries to set the bit at the same time, the bit is set. After power-up all bits are
cleared.
Figure 13-15. Abort-Acknowledge Register (CANAA)
31 0
AA[31:0]
RC-0
LEGEND: RC = Read/Clear; -n = value after reset
Table 13-14. Abort-Acknowledge Register (CANAA) Field Descriptions
Bit Field Value Description
31:0 AA[31:0] Abort-acknowledge bits
1 If the transmission of the message in mailbox n is aborted, the bit n of this register is set.
0 The transmission is not aborted.
13.8.7 Received-Message-Pending Register (CANRMP)
If mailbox n contains a received message, the bit RMP[n] of this register is set. These bits can be reset
only by the CPU and set by the internal logic. A new incoming message overwrites the stored one if the
OPC[n](OPC.31-0) bit is cleared, otherwise the next mailboxes are checked for a matching ID. If a mailbox
is overwritten, the corresponding status bit RML[n] is set. The bits in the CANRMP and the CANRML
registers are cleared by a write to register CANRMP, with a 1 at the corresponding bit location. If the CPU
tries to reset a bit and the CAN tries to set the bit at the same time, the bit is set.
The bits in the CANRMP register can set GMIF0/GMIF1 (GIF0.15/GIF1.15) if the corresponding interrupt
mask bit in the CANMIM register is set. The GMIF0/GMIF1 bit initiates an interrupt.
Figure 13-16. Received-Message-Pending Register (CANRMP)
31 0
RMP[31:0]
RC-0
LEGEND: RC = Read/Clear; -n = value after reset
Table 13-15. Received-Message-Pending Register (CANRMP) Field Descriptions
Bit Field Value Description
31:0 RMP[31:0] Received-message-pending bits
1 If mailbox n contains a received message, bit RMP[n] of this register is set.
0 The mailbox does not contain a message.

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Texas Instruments TMS320 2833 Series Specifications

General IconGeneral
BrandTexas Instruments
ModelTMS320 2833 Series
CategoryController
LanguageEnglish

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