Receiver Configuration
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SPRUI07–March 2020
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Multichannel Buffered Serial Port (McBSP)
12.8.19 SRG Clock Divide-Down Value
Table 12-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value
Register Bit Name Function Type Reset Value
SRGR1 7-0 CLKGDV Sample rate generator clock divide-down value R/W 0000 0001
The input clock of the sample rate generator is divided by
(CLKGDV + 1) to generate the required sample rate generator
clock frequency. The default value of CLKGDV is 1 (divide input
clock by 2).
12.8.19.1 Sample Rate Generator Clock Divider
The first divider stage generates the serial data bit clock from the input clock. This divider stage utilizes a
counter, preloaded by CLKGDV, that contains the divide ratio value.
The output of the first divider stage is the data bit clock, which is output as CLKG and which serves as the
input for the second and third stages of the divider.
CLKG has a frequency equal to 1/(CLKGDV + 1) of sample rate generator input clock. Thus, the sample
generator input clock frequency is divided by a value between 1 and 256. When CLKGDV is odd or equal
to 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide-down,
the high-state duration is p + 1 cycles and the low-state duration is p cycles.
12.8.20 SRG Clock Synchronization Mode
For more details on using the clock synchronization feature, see Section 12.4.3.
Table 12-44. Register Bit Used to Set the SRG Clock Synchronization Mode
Register Bit Name Function Type
Reset
Value
SRGR2 15 GSYNC Sample rate generator clock synchronization R/W 0
GSYNC is used only when the input clock source for the sample rate
generator is external—on the MCLKR or MCLKX pin.
GSYNC = 0 The sample rate generator clock (CLKG) is free
running. CLKG oscillates without adjustment, and
FSG pulses every (FPER + 1) CLKG cycles.
GSYNC = 1 Clock synchronization is performed. When a
pulse is detected on the FSR pin:
• CLKG is adjusted as necessary so that it is
synchronized with the input clock on the
MCLKR or MCLKX pin.
• FSG pulses. FSG only pulses in response to
a pulse on the FSR pin. The frame-
synchronization period defined in FPER is
ignored.
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