ADC Registers
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SPRUI07–March 2020
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Analog-to-Digital Converter (ADC)
7.4.5 ADCCHSELSEQ2 Register (Offset = 4h) [reset = 0h]
ADCCHSELSEQ2 is shown in Figure 7-19 and described in Table 7-15.
Figure 7-19. ADCCHSELSEQ2 Register
15 14 13 12 11 10 9 8
CONV07 CONV06
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CONV05 CONV04
R/W-0h R/W-0h
Table 7-15. ADCCHSELSEQ2 Register Field Descriptions
Bit Field Type Reset Description
15-12 CONV07 R/W 0h
11-8 CONV06 R/W 0h
7-4 CONV05 R/W 0h
3-0 CONV04 R/W 0h
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