www.ti.com
eCAN Registers
801
SPRUI07–March 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Controller Area Network (CAN)
13.8 eCAN Registers
This chapter contains the registers and bit descriptions.
Figure 13-9. Mailbox-Enable Register (CANME)
31 0
CANME[31:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
13.8.1 Mailbox Enable Register (CANME)
This register is used to enable/disable individual mailboxes.
Figure 13-10. Mailbox-Enable Register (CANME)
31 0
CANME[31:0]
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-9. Mailbox-Enable Register (CANME) Field Descriptions
Bit Field Value Description
31:0 CANME[31:0] Mailbox enable bits. After power-up, all bits in CANME are cleared. Disabled mailboxes can be
used as additional memory for the CPU.
1 The corresponding mailbox is enabled. The mailbox must be disabled before writing to the contents
of any identifier field. If the corresponding bit in CANME is set, the write access to the identifier of a
mailbox is denied and an interrupt (write-denied interrupt) generated, if enabled.
0 The corresponding mailbox RAM area is disabled for the eCAN; however, it is accessible to the
CPU as normal RAM.